Delta - Sigma Modulator PLLs With Dithered Divide - Ratio
نویسنده
چکیده
A phase-locked loop (PLL) with frequency resolution in steps smaller than the reference oscillator is often wanted. Although this can be accomplished with a fractional-N PLL, in which the divide ratio is varied between N and N+1 at a defined rate, this technique generates undesired spurs. An alternative is to use a delta-sigma modulator in which the divide ratio (divisor) is dithered, eliminating the spurs. This article looks at basic PLL operation, fractional-N PLL simulation, and delta-sigma PLL simulation.
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